MCP37D11-80ESLASHTE datasheet(72/136 Pages) MICROCHIP

72 / 136 page

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

DS20006381A-page 72

 2020 Microchip Technology Inc.

FIGURE 5-1:

SPI Serial Data Communication Protocol with MSb-first. See Figures 2-3 and 2-4 for

Timing Specifications.

FIGURE 5-2:

SPI Serial Data Communication Protocol - with LSb-First. See Figures 2-3 and 2-4 for

Timing Specifications.

5.1

The internal Configuration registers are initialized to

their default values under two different conditions:

• After 220 clock cycles of delay from the Power-on

Reset (POR).

• Resetting the hardware reset pin (RESET).

Figures 2-3 and 2-4 show the timing details.

5.2

Configuration Registers

The internal registers are mapped from Addresses

0x00 – 0x15D.

These

user

registers

are

not

sequentially

located.

Some

user

Configuration

registers include factory-controlled bits. The factory-

controlled bits should not be overwritten by the user.

All user Configuration registers are read/write, except

for the last four registers, which are read-only. Each

their default values are loaded during the power-up

sequence or by using the hardware RESET pin. All

registers are accessible by the SPI command using the

memory map, and Registers 5-1 – 5-83 show the

details of the register bit functions.

R/W W1 W0 A2 A1 A0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

16-Bit Instruction Header

Address of

SCLK

SDIO

defined by R9 - R0

D7 D6 D5 D4 D3 D2 D1 D0

Device Address

starting register

Starting Register

R/W

16-Bit Instruction Header

Address of

SCLK

SDIO

Device Address

defined by R9 - R0

starting register

Starting Register

Note 1: All address and bit locations that are not

included in the following register map

table should not be written or modified by

the user.

2: Some registers include factory-controlled

bits (FCB). Do not overwrite these bits.

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