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FSL518APG bảng dữ liệu(PDF) 18 Page - ON Semiconductor |
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FSL518APG bảng dữ liệu(HTML) 18 Page - ON Semiconductor |
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18 / 27 page ![]() FSL518H, FSL538H, FSL518A, FSL538A www.onsemi.com 18 Figure 40. Timing Chart of OLP IDRAIN Protection t t t t VCC VCOMP tAR VOLP VCC−STOP ILIM VCC−HVREG tD−OLP Over Voltage Protection (OVP) A malfunction of voltage-feedback circuitry for output regulation in power converter could result in excessive energy delivered to output. In this condition, both output voltage and VCC can be increased by unstable operation, and OVP will be triggered after delay time tD−OVP when VCC rises above VCC−OVP. Figure 41. Timing Chart of OVP t t tAR VCC −STOP VCC −HVREG VCC−OVP tD−OVP Fault t Protection Vcc IDRAIN Abnormal Over-Current Protection (AOCP) When the secondary-side rectifier diodes or the transformer windings are shorted, a steep drain current with extremely high di/dt will flow through the MOSFET during the minimum turn-on time. Under this condition, each switching cycle generates very high current stress on power MOSFET. The controller monitors drain current within a limited leading-edge time duration tLEB + tAOCP of each switching cycle. If drain current exceeds current limit for a few consecutive switching cycles, NAOCP-TRIG, switching will be stopped for number of pulses, NAOCP-HALT. If the fault condition is met for three times, NAOCP-COUNT, the controller goes into protection mode as shown in Fig. 42. |
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