ADRF6720ACPZ-R7 datasheet(9/44 Pages) AD

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Data Sheet

ADRF6720

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

MUXOUT

Multiplexer Output. This output allows a digital lock detect signal, a voltage

proportional to absolute temperature (VPTAT), or a buffered, frequency-scaled

reference signal to be accessed externally. The output is selected by programming

Bits[6:4] in Register 0x21.

2, 10

GND

Baseband Ground.

3, 4

I+, I−

Differential In-Phase Baseband Inputs.

5, 7

GND

Mixer Core (I and Q) Ground.

VPOS1

3.3 V Supply Voltage for Baseband. Decouple VPOS1 with 100 pF and 0.1 µF

capacitors located close to the pin.

8, 9

Q−, Q+

Differential Quadrature Baseband Inputs.

VPOS2

3.3 V Supply Voltage for 2.5 V LDO. Decouple VPOS2 with 100 pF and 0.1 µF

capacitors located close to the pin.

DECL1

Decoupling Pin for 2.5 V LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between

this pin and ground.

SDIO

Serial Data Input/Output for SPI.

SCLK

Serial Clock Input/Output for SPI.

Chip Select Input/Output for SPI.

GND

Digital Ground.

VPOS3

3.3 V Supply Voltage for LO. Decouple VPOS3 with 100 pF and 0.1 µF capacitors

located close to the pin.

18, 19

LOOUT+, LOOUT−

Differential LO Outputs. Either the internally generated LO or external 1 × LO/2 × LO

is available at 1 × LO or 2 × LO on these pins.

GND

LO Ground.

NIC

Not Internally Connected. This pin can be left open or tied to RF ground.

VPOS4

3.3 V Supply Voltage for RF. Decouple VPOS4 with 100 pF and 0.1 µF capacitors

located close to the pin.

23, 25

GND

RF Ground.

RFOUT

Single-Ended 0 V DC RF Output.

VPOS5

3.3 V Supply Voltage for RF. Decouple VPOS5 with 100 pF and 0.1 µF capacitors

located close to the pin.

ENBL

Enables/Disables the Circuit Blocks. References the settings at Register 0x01 and

DECL2

Decoupling Pin for VCO LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between

this pin and ground.

GND

VCO Ground.

1. NIC = NOT INTERNALLY CONNECTED.

MUXOUT

GND

I+

I–

GND

VPOS1

GND

Q+

Q–

GND

RFOUT

GND

VPOS5

NIC

DECL2

GND

VPOS6

VPOS4

ENBL

NOTES

2. SOLDER THE EXPOSED PAD TO A LOW IMPEDANCE

GROUND PLANE.

ADRF6720

TOP VIEW

(Not to Scale)

Rev. 0 | Page 9 of 44

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