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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADRF6720ACPZ-R7 bảng dữ liệu(PDF) 5 Page - Analog Devices |
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ADRF6720ACPZ-R7 bảng dữ liệu(HTML) 5 Page - Analog Devices |
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5 / 44 page  Data Sheet ADRF6720 Rev. 0 | Page 5 of 44 Parameter Test Conditions/Comments Min Typ Max Unit MUXOUT Output Level Low (lock detect output selected) 0.25 V High (lock detect output selected) 2.7 V MUXOUT Duty Cycle 50 % CHARGE PUMP Charge Pump Current Programmable to 250 μA, 500 μA, 750 μA, or 1000 μA 1000 μA Output Compliance Range 1 2.8 V PHASE NOISE, FREQUENCY = 940 MHz, fPFD = 38.4 MHz Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter design) 10 kHz offset −97.8 dBc/Hz 100 kHz offset −120.8 dBc/Hz 1 MHz offset −144.4 dBc/Hz 5 MHz offset −154.4 dBc/Hz 10 MHz offset −154.9 dBc/Hz 20 MHz offset −155.3 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth, with spurs 0.175 ° rms Reference Spurs fPFD −104.8 dBc fPFD × 2 −97.8 dBc fPFD × 3 −98.8 dBc fPFD × 4 −103 dBc PHASE NOISE, FREQUENCY = 1900 MHz, fPFD = 38.4 MHz Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter design) 10 kHz offset −91.5 dBc/Hz 100 kHz offset −114.5 dBc/Hz 1 MHz offset −139.9 dBc/Hz 5 MHz offset −151.4 dBc/Hz 10 MHz offset −153 dBc/Hz 20 MHz offset −153.5 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth, with spurs 0.332 ° rms Reference Spurs fPFD −102 dBc fPFD × 2 −90.8 dBc fPFD × 3 −93.6 dBc fPFD × 4 −100.5 dBc PHASE NOISE, FREQUENCY = 2140 MHz, fPFD = 38.4 MHz Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter design) 10 kHz offset −92 dBc/Hz 100 kHz offset −115.7 dBc/Hz 1 MHz offset −140.3 dBc/Hz 5 MHz offset −151.3 dBc/Hz 10 MHz offset −152.1 dBc/Hz 20 MHz offset −152.9 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth, with spurs 0.305 ° rms Reference Spurs fPFD −95.9 dBc fPFD × 2 −93.1 dBc fPFD × 3 −87.4 dBc fPFD × 4 −91.5 dBc |
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