ADRF6604ACPZ-R7 datasheet(21/32 Pages) AD

tên linh kiện	ADRF6604ACPZ-R7

Giải thích chi tiết về linh kiện	1200 MHz to 3600 MHz Rx Mixer with Integrated Fractional-N PLL and VCO

PDF	32 Pages

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21 / 32 page

Data Sheet

ADRF6604

Rev. B | Page 21 of 32

LO SELECTION LOGIC

The downconverting mixer in the ADRF6604 can be used

without the internal PLL by applying an external differential LO

to Pin 37 (LON) and Pin 38 (LOP). In addition, when using an

LO generated by the internal PLL, the LO signal can be accessed

directly at these pins. This function can be used for debugging

purposes, or the internally generated LO can be used as the LO

for a separate mixer.

The operation of the LO generation and whether LOP and LON

are inputs or outputs are determined by the logic levels applied

at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3

(LDRV) and Bit DB6 (PLEN) in Register 5. The combination of

externally applied logic and internal bits required for particular

LO functions is given in Table 9.

Table 9. LO Selection Logic

Pins1

Outputs

Pin 16 (PLL_EN)

Pin 36 (LODRV_EN)

Bit DB6 (PLEN)

Bit DB3 (LDRV)

Output Buffer

Disabled

External

Disabled

External

Disabled

External

Disabled

Internal

Enabled

Internal

Enabled

Internal

X = don’t care.

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