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STSAFE-A110 bảng dữ liệu(PDF) 26 Page - STMicroelectronics |
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STSAFE-A110 bảng dữ liệu(HTML) 26 Page - STMicroelectronics |
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26 / 36 page ![]() Electrical characteristics STSAFE-A110 26/36 DS13039 Rev 1 It is recommended to use an application that is able to manage the RESET pin through a host GPIO to force reset upon alarm detection. 5.2.3 Reset pin (external reset) The circuit is in reset state when the Reset signal available on the RESET pin is at logical level ‘0’. If this signal is low for less than tWL, it is not taken into account. When the RESET pin is floating, an external reset is not available and the device will remain in a Reset state as the pin is connected to an internal weak pull-down. When pin VCC is tied high, if the RESET pin switches from high to low and then to high again, a warm reset occurs. For more information, refer to Figure 15: Warm reset sequence on page 26. 5.2.4 Power-on and reset sequence Figure 14. Power-on and reset sequence Figure 15. Warm reset sequence Table 4. Power-on and reset sequence timings Name Description Conditions Min. Typ. Max. Units tHL Minimum time before de-asserting RESET after power-up -0 - - µs SVCC VCC rising slope (from 10% to 90% of nominal value) - 0.05 - 5 V/µs |
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