AM6421 datasheet(139/237 Pages) TI

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Table 7-29. RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode

see Figure 7-25

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

RGMII9 tosu(TD-TXC)

Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC

high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

tosu(TX_CTL-TXC)

Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC

high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

RGMII10 toh(TXC-TD)

Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC

high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

toh(TXC-TX_CTL)

Output hold time, RGMII[x]_TX_CTL valid after

RGMII[x]_TXC high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

RGMII[x]_TXC

(A)

RGMII[x]_TD[3:0]

(B)

RGMII[x] TX_CTL

(B)

RGMII9

1st Half-byte

TXERR

TXEN

2nd Half-byte

RGMII7

RGMII8

RGMII6

RGMII10

A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.

B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of

RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of

RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.

Figure 7-25. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics

- RGMII Mode

7.10.5.2 DDRSS

For more details about features and additional description information on the device (LP)DDR4 Memory

Interface, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed

Description.

Table 7-30 and Figure 7-26 present switching characteristics for DDRSS.

Table 7-30. DDRSS Switching Characteristics

see Figure 7-26

NO.

PARAMETER

DDR TYPE

MIN

MAX

UNIT

tc(DDR_CKP/

DDR_CKN)

Cycle time, DDR_CKP and DDR_CKN

LPDDR4

1.25

DDR4

1.25

1.6

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