AM6421 datasheet(123/237 Pages) TI

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11.VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/

down sequences and during normal device operation. This supply shall only be sourced while programming

eFuse.

7.10.2.3 Power-Down Sequencing

Figure 7-4 describes the device power-down sequencing.

AM64x_ELCH_02

MCU_PORz

MCU_OSC0_XI, MCU_OSC0_XO

VSYS

VMON_VSYS

VSYS, VMON_VSYS

VPP

VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,

VDDSHV4 , VDDSHV5 , VDDA_3P3_SDIO, VDDA_USB0,

VMON_3P3_SOC, VMON_3P3_MCU

(1)

VDDS_OSC, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,

VDDSHV4 , VDDSHV5 , VDDA_MCU, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1,

VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_MCU,

VMON_1P8_SOC, VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0

(2)

VDDS_DDR, VDDS_DDR_C

VDD_CORE

(3)

VDD_CORE , VDDR_CORE, VDDA_0P85_SERDES0_C,

VDDA_0P85_SERDES0, VDDA_0P85_USB0,

VDD_DLL_MMC0, VDD_MCU0

(4)

Hi-Z

Figure 7-4. Power-Down Sequencing

1. VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 3.3V.

2. VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 1.8V.

3. VDD_CORE when operating at 0.75V.

4. VDD_CORE when operating at 0.85V.

7.10.3 System Timing

For more details about features and additional description information on the subsystem multiplexing signals,

see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

Table 7-3. System Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

2 V/ns

OUTPUT CONDITIONS

Output load capacitance

30 pF

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AM6442, AM6441, AM6421

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SPRSP56 – JANUARY 2021

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