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STPMIC1APQR bảng dữ liệu(PDF) 99 Page - STMicroelectronics

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6.5
Interrupt registers
6.5.1
Overall interrupt register behavior
No interrupts are stored before RSTn is released. Interrupt registers are all cleared and masked on default and
turn-OFF conditions.
Section 6.5.2 Interrupt pending register 1 (INT_PENDING_R1), Section 6.5.3 Interrupt pending
register 2 (INT_PENDING_R2), Section 6.5.4 Interrupt pending register 3 (INT_PENDING_R3) and
Section 6.5.5 Interrupt pending register 4 (INT_PENDING_R4) store information about masked and not masked
events.
Section 6.5.10 Interrupt clear mask registers (INT_CLEAR_MASK_Rx) or Section 6.5.6 Interrupt debug latch
registers (INT_DBG_LATCH_Rx) is a write register. Any read on this address provides x00 as data. Writing ‘1’ in a
bit forces INT_PENDING corresponding bit to ‘1’. Writing ‘0’ has no effect.
Section 6.5.8 Interrupt mask registers (INT_MASK_Rx) is a read/write register.
INTn pin is forced low as long as a bit is set in INT_PENDING_Rx and no mask in its corresponding
Section 6.5.8 Interrupt mask registers (INT_MASK_Rx). Section 6.5.11 Interrupt source register 1
(INT_SRC_R1), Section 6.5.12 Interrupt source register 2 (INT_SRC_R2), Section 6.5.13 Interrupt source
register 3 ( INT_SRC_R3) and Section 6.5.14 Interrupt source register 4 ( INT_SRC_R4) reflects a ‘real time’
status of the event while INT_PENDING_Rx stores events and not levels.
STPMIC1
Interrupt registers
DS12792 - Rev 7
page 99/140



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