STPMIC1APQR datasheet(55/140 Pages) STMICROELECTRONICS

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Name

Conditions

Power cycle if

RREQ_EN=1

Default value loaded by PKEYLKP_OFF bit in

Table 65. NVM_MAIN_CTRL_SHR

Request duration for the long key press defined in PKEY_LKP_TMR[3:0] in

Table 31. PKEY_TURNOFF_CR

PONKEYn signal is asserted for a duration > PKEY_LKP_TMR[3:0]

Thermal shutdown

STPMIC1 functional temperature is exceeded. Refer to

Section 5.4.6 Thermal protection

STPMIC1 always restart

automatically whatever

restart_request option.

Overcurrent

protection

STPMIC1 detects overcurrent on a regulator. Refer to

Section 5.4.7 Overcurrent protection (OCP)

Watchdog

Watchdog feature active and downcounter reach 0. Refer to

Section 5.4.9 Watchdog feature

YES

VIN_OK_Fall

VIN falls down under VIN_OK_Fall threshold.

Depending on VIN decrease speed, proper execution of POWER_DOWN

operation is not guaranteed

YES only if VIN remains

above POR_VIN_Fall

Last turn-OFF condition is stored in Table 20. TURN_OFF_SR.

If restart_request is set, power cycle source is stored in Table 23. RESTART_SR register.

5.4.4

Reset and mask_reset option

RSTn is bidirectional reset pin both for the STPMIC1 and the application processor. It is digital input / open drain

output topology with internal pull-up resistor.

•

When the STPMIC1 asserts RSTn, it drives RSTn signal low (open drain internal transistor). Application

processor is forced in reset state

•

When the STPMIC1 does not assert RSTn, RSTn pin is in high impedance and RSTn signal goes high

(thanks to pull-up resistor) if RSTn signal is not asserted low externally (eg: by a reset push button or from

application processor asserting the reset signal low). In that case, the STPMIC1 RSTn pin becomes digital

input and it monitors RSTn signal

In POWER_ON state, RSTn pin can be driven by the application processor or a reset push-button.

If the application processor asserts RSTn low more than RSTnDB duration, it triggers immediately a reset

sequence of the STPMIC1 by performing a non-interruptible power cycle:

The STPMIC1 asserts RSTn low (forcing AP to keep it in case reset is deasserted by AP)

POWER_DOWN sequence

LOAD&CHECK

POWER_UP sequence

STPMIC1 deasserts RSTn and monitor RSTn

STPMIC1 waits for RSTn signal going high before entering POWER_ON. (To prevent infinite loop of reset

sequence)

LDOs and Bucks follow POWER_DOWN / POWER_UP power cycle from leave state to default one, except if

mask_reset option is specified.

mask_reset option can be defined for each regulator by setting the corresponding MRST bit in corresponding

MRST_CR register.

Eg for BUCK3 : MRST_BUCK3 in Table 32. BUCKS_MRST_CR.

When mask_reset option is set by a regulator, it means that MAIN and ALTERNATE related register do not

change during and after the reset power cycle:

•

POWER_DOWN is not performed

•

MAIN and ALTERNATE register values are not reloaded by NVM and are not reset

The STPMIC1 always ends the power cycle in POWER_ON MAIN mode. (PWRCTRL pin configuration reset).

If reset happens in MAIN mode, the regulator is not impacted at all, keeping VOUT, ENA and PREG_MODE

unchanged.

STPMIC1

Feature description

DS12792 - Rev 7

page 55/140

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