STM32WB35CCU6ATR datasheet(69/193 Pages) STMICROELECTRONICS

69 / 193 page

DS11929 Rev 10

69/193

STM32WB55xx STM32WB35xx

Pinouts and pin description

46 66

PB6

I/O FT_fla

LPTIM1_ETR, I2C1_SCL,

USART1_TX, TSC_G2_IO3,

LCD_SEG6, SAI1_FS_B,

TIM16_CH1N, MCO,

CM4_EVENTOUT

COMP2_INP

47 67 D7

PB7

I/O FT_fla

LPTIM1_IN2, TIM1_BKIN,

I2C1_SDA, USART1_RX,

TSC_G2_IO4, LCD_SEG21,

TIM17_CH1N,

CM4_EVENTOUT

COMP2_INM, PVD_IN

VSS

VSS_DCAP4

48 68 A10

VDD

VDD_DCAP4

VDD_DCAP1

J12

VDD_DCAP3

VDD_DCAP2

1. PC13, PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA),

the use of the PC13, PC14 and PC15 GPIOs in output mode is limited:



- the speed must not exceed 2 MHz with a maximum load of 30 pF



- these GPIOs must not be used as current sources (e.g. to drive a LED).

2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of

the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup

domain and RTC register descriptions in the reference manual RM0434, available on www.st.com.

3. The clock on LSCO is available in Run and Stop modes, and on PA2 in Standby and Shutdown modes.

4. On UFQFPN48 VDDA is connected to VREF+.

5. RF pin, use the nominal PCB layout.

6. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165).

7. Reserved, must be kept unconnected.

8. High frequency (above 32 kHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0 and

1) during RF operation.

9. After reset these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and

PB4 pins and the internal pull-down on PA14 pin are activated.

Table 16. STM32WB55xx pin and ball definitions (continued)

Pin number

Pin name

(function after

reset)

Alternate functions

Additional functions

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