STM32L552CCT3PTR datasheet(26/340 Pages) STMICROELECTRONICS

26 / 340 page

Functional overview

STM32L552xx

26/340

DS12737 Rev 6

3.7

Global TrustZone controller (GTZC)

The GTZC includes three different sub-blocks:

•

TZSC: TrustZone® security controller

This sub-block defines the secure/privilege state of slave/master peripherals. It also

controls the non-secure area size for the watermark memory peripheral controller

(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about

the secure status of each securable peripheral, by sharing with RCC and I/O logic.

MPCBB: block-based memory protection controller

This sub-block controls secure states of all blocks (256-byte pages) of the associated

SRAM.

TZIC: TrustZone illegal access controller

This sub-block gathers all illegal access events in the system and generates a secure

interrupt towards NVIC.

These sub-blocks are used to configure TrustZone and privileged attributes within the full

system.

The GTZC main features are:

•

3 independent 32-bit AHB interface for TZSC, MPCBB and TZIC

•

MPCBB and TZIC accessible only with secure transactions

•

Secure and non-secure access supported for priv/non-priv part of TZSC

•

–

Secure blocks for internal SRAM

–

Non-secure regions for external memories

–

Secure/privilege access mode for securable and TZ-aware peripherals

•

Secure/privilege access mode for securable legacy masters.

0.5

Boot address only in:

– RSS

– or secure Flash: 0x0C00 0000 -

0x0C07 FFFF

Otherwise boot address forced to RSS

N/A

Any boot address

If boot is configured for NSBOOTADD0 and

NSBOOTADD0 in the range 0x0800 0000 -

0x0807 FFFF: boot at the address stored in

NSBOOTADD0

If boot is configured for NSBOOTADD1 and

NSBOOTADD1 in the range 0x0800 0000 -

0x0807 FFFF: boot at the address stored in

NSBOOTADD1

Otherwise boot address is forced at

0x0800 0000

Table 5. Boot space versus RDP protection (continued)

RDP

TZEN = 1

TZEN = 0

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