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STM32L552CCT3PTR bảng dữ liệu(PDF) 191 Page - STMicroelectronics |
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STM32L552CCT3PTR bảng dữ liệu(HTML) 191 Page - STMicroelectronics |
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191 / 340 page ![]() Table 71. Current consumption in Run mode, code with data processing running from Flash, ICACHE on (2-way) and power supplied by external SMPS Symbol Parameter Conditions(1) TYP single bank mode TYP single bank mode Unit TYP single bank mode TYP single bank mode Unit - VDD12 fHCLK code 25°C 25°C 25°C 25°C IDD(Run) Supply current in Run mode fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled VDD12=1.00V fHCLK=26MHz Reduced code 1.2 1.2 mA 46.15 46.15 µA/MHz Coremark 1.29 1.29 49.62 49.62 Dhrystone2.1 1.37 1.37 52.69 52.69 Fibonacci 1.15 1.14 44.23 43.85 While(1) 1.04 1.04 40 40 VDD12=1.10V fHCLK=26MHz Reduced code 1.45 1.45 mA 55.77 55.77 µA/MHz Coremark 1.56 1.56 60 60 Dhrystone2.1 1.66 1.65 63.85 63.46 Fibonacci 1.39 1.38 53.46 53.08 While(1) 1.26 1.26 48.46 48.46 fHCLK=80MHz Reduced code 4.1 4.09 mA 51.25 51.13 µA/MHz Coremark 4.4 4.4 55 55 Dhrystone2.1 4.7 4.68 58.75 58.5 Fibonacci 3.88 3.88 48.5 48.5 While(1) 3.55 3.55 44.38 44.38 VDD12=1.20V fHCLK=110MHz Reduced code 6.69 6.69 mA 60.82 60.82 µA/MHz Coremark 7.2 7.2 65.45 65.45 Dhrystone2.1 7.66 7.62 69.64 69.27 Fibonacci 6.32 6.32 57.45 57.45 While(1) 5.8 5.8 52.73 52.73 1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%. |
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