8SF3P6TR datasheet(24/103 Pages) STMICROELECTRONICS

24 / 103 page

Pinouts and pin descriptions

STM8S003F3 STM8S003K3

24/103

DS7147 Rev 10

PC4/TIM1_CH4/C

LK_CCO

I/O X

XX HS O3 X

X Port C4

Timer 1 -

channel

4/configurable

clock output

PC5/SPI_SCK

I/O X

XX HS O3 X

X Port C5 SPI clock

PC6/SPI_MOSI

I/O X

XX HS O3 X

X Port C6

SPI master

out/slave in

PC7/SPI_MISO

I/O X

XX HS O3 X

X Port C7

SPI master in/

slave out

PD0/[TIM1_BKIN

[CLK_CCO]

I/O X

XX HS O3 X

X Port D0

Timer 1 - break

input

Configurable

clock output

[AFR5]

PD1/SWIM(4)

I/O X

XHS O4 X

X Port D1

SWIM data

interface

PD2

[TIM2_CH3]

I/O X

XX HS O3 X

X Port D2

Timer 2 -

channel 3

[AFR1]

PD3/TIM2_CH2

[ADC_ETR]

I/O X

XX HS O3 X

X Port D3

Timer 2 -

channel 2/ADC

external trigger

PD4/BEEP/

TIM2_CH1

I/O X

XX HS O3 X

X Port D4

Timer 2 -

channel

1/BEEP output

PD5/ UART1_TX I/O X

XX HS O3 X

X Port D5

UART1 data

transmit

PD6/ UART1_RX I/O X

XX HS O3 X

X Port D6

UART1 data

receive

PD7/TLI

[TIM1_CH4]

I/O X

XX HS O3 X

X Port D7

Top level

interrupt

Timer 1 -

channel 4

[AFR6]

1. I/O pins used simultaneously for high-current source/sink must be uniformly spaced around the package. In

addition, the total driven current must respect the absolute maximum ratings given in Section 9: Electrical

characteristics.

2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and

cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is

recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.

3. In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection

diode to VDD are not implemented).

4. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.

Table 5. STM8S003K3 descriptions (continued)

Pin name

Input

Output

Default

alternate

function

Alternate

function

after remap

[option bit]

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