39 / 129 page
SPI (Serial Peripheral Interface)
34
PRELIMINARY V1.8
TABLE 25.
Description of SPICR
11.6.
SPI Status Register (SPI1SR)
TABLE 26.
SPI Status Register (SPI1SR)
Name
Bit
Description
SPIE
7
SPIE: Serial Peripheral Interrupt Enable
0 = Disables internal SPI interrupt (SPIF)
1 = Enables internal SPI interrupt (SPIF
SPE
6
SPE: Serial Peripheral System Enable
0 = Turn off SPI system (P1.5-P1.7 can be general purpose)
1 = Turn on SPI system (P1.5-P1.7 are for SPI)
Reserved [5:4]
5-4
CPOL
3
CPOL: Clock Polarity
0 = Idle state for clock is high
1 = Idle state for clock is low
CPHA
2
CPHA: Clock Phase
0 = Transmit data on falling edge and receive data on rising edge
1 = Transmit data on rising edge and receive data on falling edge
When CPHA = 0, as soon as SS (Slave Select in slave device) goes low, the transaction
begins and data will be sampled on first edge of SCK. When CPHA = 1, the SS (Slave
Select in slave device) may be thought of as simple enable control.
SPR[1:0]
1 to 0
SPR1 and SPR0: SPI Clock Rate Select:
00 = Fclk/2
01 = Fclk/4
10 = Fclk/16
11 = Fclk/64
Address
F3H
Bit Addr.
BIT
7
6
5
4
3
2
1
0
NAME
SPIF
WCOL
Definition
SPI Trans-
fer Com-
plete
SPI Write
Collision
Detect
Reset
Value
0
0
0
0
0
0
0
0
Read/Write
by Software
R/W
R/W
R
R
R
R
R
R
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
