Capture Timers 1/2
PRELIMINARY V1.8
23
TABLE 15.
Definition of CTnCNTL (n = 1 or 2)
TABLE 16.
The Description of CTnCNTH & CTnCNTL
9.8.
C-Timer Data Register (CT1DATH & CT1DATL / CT2DATH &
CT2DATL)
Reset
Value
0
0
0
0
0
0
0
0
Read/
Write by
Software
R
R
R
R
R
R
R
R
Write by
Hardware
Written
with a new
count
value
0 or 1.
0 by
CTnCNTL
R.
Written
with a new
count
value
0 or 1.
0 by
CTnCNTL
R.
Written
with a new
count
value
0 or 1.
0 by
CTnCNTL
R.
Written
with a new
count
value
0 or 1.
0 by
CTnCNTL
R.
Written
with a new
count
value
0 or 1.
0 by
CTnCNTL
R.
Written
with a new
count
value
0 or 1.
0 by
CTnCNTL
R.
Written
with a new
count
value
0 or 1.
0 by
CTnCNTL
R.
Written
with a new
count
value
0 or 1.
0 by
CTnCNTL
R.
Name
Bit
Description
CTnCNTH[7:0] &
CTnCNTL[7:0]
15 to 0
C-Timer-n CouNTer bits
[Auto-Reload Mode]
A Modulo-N (0000H to N-1) up-counter. N is the content of CTnDATH &
CTnDATL. This counter counts up from 0000H to N-1. Then, the counter will go
back to 0000H and the comparator will generate match signal. The Match signal
will issue an interrupt request. The counter will not stop after the Match. Thus,
any C-Timer will generate continuous Match signals with a fixed period.
[Capture Mode]
A Modulo-65536 (0000H to 65535) up-counter. This counter counts up from
0000H to 65535. Then, the counter will go back to 0000H and the CTnINT will be
set to high. The counter will not stop after the overflow. Thus, any C-Timer over-
flow will generate continuous interrupt request with a fixed period.
[Up Down-Count Mode] (Capture-Timer1 only)
A Modulo-65536 (0000H to 65535) up and down-counter. This counter counts
up on the negative edge of CPTRU1 and counts down on the negative edge of
CPTRD1. Either the overflow or the underflow will set CTnINT bit. The counter
will not stop after the overflow or the underflow. Thus, any C-Timer1 overflow
and underflow will generate continuous interrupt request.
Address
D5H/E5H
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