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SPI (Serial Peripheral Interface)
PRELIMINARY V1.8
31
Figure 10.
SPI Timing Diagram
11.4.
SPI Operation
The SPI has a shift register and a receive buffer. The shift register shifts data in and out
of the device. The data byte transmitted is replaced by the data byte received. The SPI
data register(SPI1DAT) actually represents two distinct devices. Writes to SPI1DAT
are writes to the shift register itself. On the other hand, reads of SPI1DAT do not read
from the shift register, but rather from a buffer register which is automatically loaded
from the shift register upon the completion of a data transfer. This double buffering
allows the next data byte to start reception before reading the data that was just received.
Any write to the SPI1DAT during data transfer will be ignored, and will cause the write
collision(WCOL) status bit in the SPI1SR to be set. After the data transfer is completed,
internal interrupt is generated and the SPIF flag of the SPI1SR is set. Clock is generated
and data is shifted as soon as data is written to the shift register.
SS (Slave)
SCK
(CPOL=0,
CPHA=0 )
SCK
(CPOL =0,
CPHA =1)
SCK
(CPOL =1,
CPHA =0 )
SCK
(CPOL =1,
CPHA =1)
MI/MO
bit7
(MSB)
(LSB)
Strobe for
data capture
(all modes)
bit0
bit1
bit2
bit3
bit4
bit5
bit6
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