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External Interrupts
96
PRELIMINARY V1.8
TABLE 70.
Internal Priority and Vector Address
TABLE 71.
Definition of IP
15.3.4
Interrupt Processing
The interrupt request flags are sampled at S5P2 of every machine cycle. The samples
are polled during the following machine cycle. If one of the flags was in a set condition
at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system
will generate an LCALL to the appropriate service routine, provided this hardware
generated LCALL is blocked by any of the following conditions:
1. An interrupt of equal or higher priority level is already in progress
2. The current polling cycle is not the final cycle in the execution of the instruction in
progress
3. The instruction in progress is RETI.
4. The instruction in progress is any access to the IE or IP registers.
Any of these four conditions will block the generation of the LCALL to the interrupt
service routine. Condition 2 ensures that the instruction in progress will be completed
5
Group-E
TBINT/CT1INT/CT2INT
0023H
Lowest
Address
B8H
Bit Addr.
BFH
BEH
BDH
BCH
BBH
BAH
B9H
B8H
BIT
7
6
5
4
3
2
1
0
NAME
PGE
PGD
PGC
PGB
PGA
Definition
Reserved
bit
Reserved
bit
Reserved
bit
Priority of
Group-E
1: High
Priority
0: Low
Priority
Priority of
Group-D
1: High
Priority
0: Low
Priority
Priority of
Group-C
1: High
Priority
0: Low
Priority
Priority of
Group-B
1: High
Priority
0: Low
Priority
Priority of
Group-A
1: High
Priority
0: Low
Priority
Reset Value
unknown
unknown
unknown
0
0
0
0
0
Read/Write
by Software
R/W
R/W
R/W
R/W
R/W
Write
by Hardware
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