XIO2001IPNP datasheet(110/144 Pages) TI

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110

XIO2001

SCPS212I – MAY 2009 – REVISED JANUARY 2016

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Table 81. Serial IRQ Status Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

4(1)

IRQ4

RCU

IRQ 4 asserted. This bit indicates that the IRQ4 has been asserted.

0 = Deasserted

1 = Asserted

3(1)

IRQ3

RCU

IRQ 3 asserted. This bit indicates that the IRQ3 has been asserted.

0 = Deasserted

1 = Asserted

2(1)

IRQ2

RCU

IRQ 2 asserted. This bit indicates that the IRQ2 has been asserted.

0 = Deasserted

1 = Asserted

1(1)

IRQ1

RCU

IRQ 1 asserted. This bit indicates that the IRQ1 has been asserted.

0 = Deasserted

1 = Asserted

0(1)

IRQ0

RCU

IRQ 0 asserted. This bit indicates that the IRQ0 has been asserted.

0 = Deasserted

1 = Asserted

8.6.12 Pre-Fetch Agent Request Limits Register

This register is used to set the Pre-Fetch Agent's limits on retrieving data using upstream reads. This register is

an alias for the pre-fetch agent request limits register in the classic PCI configuration space (offset E8h, see Pre-

Fetch Agent Request Limits Register). See Table 82 for a complete description of the register contents.

Device control memory window register offset:

50h

Read/Clear

Default value:

0443h

BIT NUMBER

RESET STATE

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Table 82. Pre-Fetch Agent Request Limits Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:12

RSVD

Reserved. Returns 0h when read.

11:8(1)

PFA_REQ_

CNT_LIMIT

Request count limit. Determines the number of Pre-Fetch reads that takes place in each

burst.

4'h0 = Auto-prefetch agent is disabled.

4'h1 = Thread is limited to one buffer. No auto-prefetch reads will be generated.

4'h2:F = Thread will be limited to initial read and (PFA_REQ_CNT_LIMIT – 1)

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