XIO2001IPNP datasheet(48/144 Pages) TI

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XIO2001

SCPS212I – MAY 2009 – REVISED JANUARY 2016

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8.4.8 Primary Latency Timer Register

This read-only register has no meaningful context for a PCI Express device and returns 00h when read.

PCI register offset:

0Dh

Read only

Default value:

00h

BIT NUMBER

RESET STATE

8.4.9 Header Type Register

This read-only register indicates that this function has a type one PCI header. Bit 7 of this register is 0b indicating

that the bridge is a single-function device.

PCI register offset:

0Eh

Read only

Default value:

01h

BIT NUMBER

RESET STATE

8.4.10 BIST Register

Since the bridge does not support a built-in self test (BIST), this read-only register returns the value of 00h when

read.

PCI register offset:

0Fh

Read only

Default value:

00h

BIT NUMBER

RESET STATE

8.4.11 Device Control Base Address Register

This register programs the memory base address that accesses the device control registers. By default, this

set, then the bits 31:12 of this register become read/write. See Table 15 for a complete description of the register

contents.

PCI register offset:

10h

Read-only, Read/Write

Default value:

0000 0000h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

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