XIO2001IPNP datasheet(64/144 Pages) TI

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XIO2001

SCPS212I – MAY 2009 – REVISED JANUARY 2016

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8.4.47

PCI Express Capability ID Register

This read-only register identifies the linked list item as the register for subsystem ID and subsystem vendor ID

capabilities. The register returns 10h when read.

PCI register offset:

70h

Read-only

Default value:

10h

BIT NUMBER

RESET STATE

8.4.48 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

PCI register offset:

71h

Read-only

Default value:

00h

BIT NUMBER

RESET STATE

8.4.49 PCI Express Capabilities Register

This read-only register indicates the capabilities of the bridge related to PCI Express. See Table 34 for a

complete description of the register contents.

PCI register offset:

72h

Read-only

Default value:

0072h

BIT NUMBER

RESET STATE

Table 34. PCI Express Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:14

RSVD

Reserved. Returns 00b when read.

13:9

INT_NUM

Interrupt message number. This field is used for MSI support and is implemented as read-

only 00000b in the bridge.

SLOT

Slot implemented. This bit is not valid for the bridge and is read-only 0b.

7:4

DEV_TYPE

Device/port type. This read-only field returns 0111b indicating that the device is a PCI

Express-to-PCI bridge.

3:0

VERSION

Capability version. This field returns 2h indicating revision 2 of the PCI Express capability.

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