PCF8545ATT datasheet(4/54 Pages) NXP

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PCA85233

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Product data sheet

Rev. 5 — 12 November 2018

4 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

Pinning information

6.1 Pinning

6.2 Pin description

[1]

The substrate (rear side of the die) is at VSS potential and should be electrically isolated.

Viewed from active side. For mechanical details, see Figure 27.

Fig 3.

Pin configuration for PCA85233

Table 4.

Pin description overview

Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.

Symbol

Description

SDAACK

1 to 3

I2C-bus acknowledge output

SDA

4 to 6

I2C-bus serial data input

SCL

7 to 9

I2C-bus serial clock input

CLK

clock input and output

VDD

11 to 13

supply voltage

SYNC

cascade synchronization input or output; if not

used it must be left open

OSC

oscillator select

frame frequency select

A0, A1

17, 18

subaddress input

dedicated testing pin; to be tied to VSS in

application mode

SA0

I2C-bus slave address input

VSS[1]

21 to 23

ground supply voltage

VLCD

24 to 26

LCD supply voltage

BP2, BP0, BP3, and BP1

27, 28, 109 and 110

LCD backplane output

S0 to S79

29 to 108

LCD segment output

D1 to D9

dummy pins

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