ADSP21486KSWZ3ABRL datasheet(49/71 Pages) AD

49 / 71 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. H

Page 49 of 71

February 2020

SPI Interface—Master

The ADSP-2148x contains two SPI ports. Both primary and sec-

ondary are available through DPI only. The timing provided in

Table 49 and Table 50 applies to both.

Table 49. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

tSSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time)

8.2

tHSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid

Switching Characteristics

tSPICLKM

Serial Clock Cycle

8 × tPCLK – 2

tSPICHM

Serial Clock High Period

4 × tPCLK – 2

tSPICLM

Serial Clock Low Period

4 × tPCLK – 2

tDDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time)

2.5

tHDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

4 × tPCLK – 2

tSDSCIM

DPI Pin (SPI Device Select) Low to First SPICLK Edge

4 × tPCLK – 2

tHDSM

Last SPICLK Edge to DPI Pin (SPI Device Select) High

4 × tPCLK – 2

tSPITDM

Sequential Transfer Delay

4 × tPCLK – 1.2

Figure 34. SPI Master Timing

tSPICHM

tSDSCIM

tSPICLM

tSPICLKM

tHDSM

tSPITDM

tDDSPIDM

tHSPIDM

tSSPIDM

DPI

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

CPHASE = 1

CPHASE = 0

tHDSPIDM

tHSPIDM

tSSPIDM

tDDSPIDM

tHDSPIDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

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