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MPF5024AMMA0ES bảng dữ liệu(PDF) 79 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  Power management integrated circuit (PMIC) for high performance applications
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MPF5024AMMA0ES bảng dữ liệu(HTML) 79 Page - NXP Semiconductors

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NXP Semiconductors
PF5024
Power management integrated circuit (PMIC) for high performance applications
PF5024
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1 — 15 April 2020
79 / 93
aaa-028077
LP_Off
QPU_Off
PWRON
event
PWRON
event
Self-Test
POWER UP
POWER OFF
SYSTEM ON
FUSE LOAD
Vin > UVDET
Default
Config
OTP
Config
I2C Register
Map
TBB Default
Configuration
Hardwire
Power up Configuration
lf TBBEN = V1P5D
(Limited Functionality)
lf TBBEN = GND
(Full Functionality)
TBBEN = V1P5D
· WDI disabled
· Watchdog Disabled
· l2C CRC disabled
· l2C Address = 0x08
· Access Miscellaneous
Debug flags
VDDOTP = V1P5D
I2C Register
Map
I2C Register
Map
Mirror
Registers
Mirror
Registers
Figure 33. Hardwire operation diagram
For simplicity, the default hardwire configuration in PF5024 is organized based on the
OTP register map as shown in Table 58.
Table 58. Default hardwire configuration
ADDR
Register Name
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Configuration
A0
OTP I2C
0
0
0
0
0
0
0
0
Secured I2C disabled | I2C CRC disabled | I2C address =
0x08
A1
OTP CTRL1
0
0
0
0
0
0
1
0
EWARN_TIME = 100 µs | Fail-safe state enabled |
STANDBY active high | PGOOD indicator | RESETBMCU
is not influenced by power-up
A2
OTP CTRL2
0
0
0
0
0
1
0
1
XFAIL = disabled | VIN_OVLO shutdown disabled | VIN_
OVLO enabled | VIN_OVLO debounce = 100 µs



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