MPF5024AMMA0ES datasheet(43/93 Pages) NXP

43 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

43 / 93

If a PWRON event is present, the device will start a turn on event and proceed to release

the XFAILB pin when its ready to start the power up sequence state. If the XFAILB pin

is pulled down externally during the power up event, the PF5024 will stop the power up

sequence until the pin is no longer pulled down externally. This will help both PMICs to

synchronize the power up sequence allowing it to continue only when both PMICs are

ready to initiate the power up sequence.

A hard WD event will set the XFAILB pin 20 µs before it starts its power down sequence.

After all regulator outputs have been turned off, the device will release the XFAILB pin

internally after a 30 µs delay, proceed to load the default OTP configuration and wait for

the XFAILB pin to be released externally before it can restart the power up sequence.

aaa-029989

Self-Test QPU_Off

System On

LP_Off

Power Up

Sequence

Bidirectional XFAILB (Power UP)

PWRON

States

XFAILB

RESETBMCU

POWER UP

Sequence

Figure 18. XFAILB behavior during a power up sequence

aaa-029990

System On

Off Mode

Power Down

Sequence

Bidirectional XFAILB (Power Down)

FAULT EVENT

EWARN

States

XFAILB

POWER DOWN

Signal

POWER DOWN

Sequence

20 µs

100 µs

Figure 19. XFAILB behavior during a power down sequence

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