MPF5023AMMA0ES datasheet(68/91 Pages) NXP

68 / 91 page

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

PF5023

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Product data sheet

Rev. 1 — 15 April 2020

68 / 91

WD_EVENT_CNT

reset by Fail-safe

Transition

WD_EVENT_CNT

reset by MCU

aaa-028075

WD_EVENT_CNT

WD EVENT

FAIL-SAFE

TRANSITION

n =

WD_MAX

_CNT

Figure 31. Watchdog event counter

16 I2C register map

The PF5023 provides a complete set of registers for control and diagnostics of the PMIC

operation. The configuration of the device is done at two different levels.

At first level, the OTP mirror registers provide the default hardware and software

configuration for the PMIC upon power up. These are one-time programmable and

should be defined during the system development phase, and are not meant to be

modified during the application. See Section 17 "OTP/TBB and hardwire default

configurations" for the OTP configuration feature.

At a second level, the PF5023 provides a set of functional registers intended for

system configuration and diagnostics during the system operation. These registers are

accessible during the system On state and can be modified at any time by the system

control unit.

The device ID register provides general information about the PMIC:

• DEVICE_FAM[3:0]: indicates the PF50x0 family of devices.

0101 (fixed)

• DEVICE_ID[3:0]: provides the device type identifier

0011 = PF5023 QM

1011 = PF5023 ASIL B

Registers 0x02 and 0x03 provide a customizable program ID registers to identify the

specific OTP configuration programmed in the part.

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