MSP430F6435IPZR datasheet(18/128 Pages) TI

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8 Specifications

All graphs in this section are for typical conditions, unless otherwise noted.

Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

MIN

MAX

UNIT

Voltage applied at VCC to VSS

–0.3

4.1

Voltage applied to any pin (excluding VCORE, VBUS, V18)(2)

–0.3

VCC + 0.3

Diode current at any device pin

±2

Maximum junction temperature, TJ

°C

Storage temperature, Tstg (3)

–55

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3)

Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

8.2 ESD Ratings

VALUE

UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±1000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±250

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as

±250 V may actually have higher performance.

8.3 Recommended Operating Conditions

MIN

NOM

MAX UNIT

VCC

Supply voltage during program execution and flash

programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =

DVCC = VCC)(1) (2)

PMMCOREVx = 0

1.8

3.6

PMMCOREVx = 0, 1

2.0

3.6

PMMCOREVx = 0, 1, 2

2.2

3.6

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

VSS

Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =

DVSS2 = DVSS3 = VSS)

VBAT,RTC

Backup-supply voltage with RTC operational

TA = 0°C to 85°C

1.55

3.6

TA = –40°C to +85°C

1.70

3.6

VBAT,MEM

Backup-supply voltage with backup memory retained

TA = –40°C to +85°C

1.20

3.6

Operating free-air temperature

I version

–40

°C

Operating junction temperature

I version

–40

°C

CBAK

Capacitance at pin VBAK

4.7

CVCORE

Capacitor at VCORE(4)

470

CDVCC/

CVCORE

Capacitor ratio of DVCC to VCORE

fSYSTEM

Processor frequency (maximum MCLK frequency)(3) (5)

(see Figure 8-1)

PMMCOREVx = 0,

1.8 V ≤ VCC ≤ 3.6 V

(default condition)

8.0

MHz

PMMCOREVx = 1,

2 V ≤ VCC ≤ 3.6 V

12.0

MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433

SLAS720F – AUGUST 2010 – REVISED SEPTEMBER 2020

www.ti.com

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