MSP430F6435IPZR datasheet(68/128 Pages) TI

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9.12.9 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention.

For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM.

Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces

system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move

data to or from a peripheral. Table 9-11 lists the trigger assignments for each DMA channel.

Table 9-11. DMA Trigger Assignments

TRIGGE

R(1)

CHANNEL

DMAREQ

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA2CCR2 CCIFG

TBCCR0 CCIFG

TBCCR2 CCIFG

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

DAC12_0IFG(2)

DAC12_1IFG(2)

Reserved

MPY ready

DMA5IFG

DMA0IFG

DMA1IFG

DMA2IFG

DMA3IFG

DMA4IFG

DMAE0

(1)

Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not

cause any DMA trigger event when selected.

(2)

Only on devices with peripheral module DAC12_A. Reserved on devices without DAC.

9.12.10 Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as

MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433

SLAS720F – AUGUST 2010 – REVISED SEPTEMBER 2020

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