STM32F722IC datasheet(164/229 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F722xx STM32F723xx

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DS11853 Rev 6

Figure 52. 12-bit buffered /non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external

loads directly without the use of an external operational amplifier. The buffer can be bypassed by

configuring the BOFFx bit in the DAC_CR register.

6.3.29

Communications interfaces

I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user

manual rev. 03 for:

•

Standard-mode (Sm): with a bit rate up to 100 kbit/s

•

Fast-mode (Fm): with a bit rate up to 400 kbit/s.

•

Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly

configured (refer to RM0431 reference manual) and when the I2CCLK frequency is greater

than the minimum shown in the table below:

tWAKEUP(4)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

6.5

µs

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

input code between lowest and highest

possible ones.

PSRR+ (2)

Power supply rejection ratio

(to VDDA) (static DC

measurement)

–67

–40

dB No RLOAD, CLOAD = 50 pF

1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:

Internal reset OFF).

2. Guaranteed by design.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic

consumption occurs.

4. Guaranteed by characterization results.

Table 78. DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max

Unit

Comments

R L

C L

Buffered/Non-buffered DAC

DAC_OUTx

Buffer(1)

12-bit

digital to

analog

converter

ai17157V3

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