MCP2517FD datasheet(63/98 Pages) MICROCHIP

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 2017-2018 Microchip Technology Inc.

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DS20005688B-page 63

MCP2517FD

3.3

Message Memory

The MCP2517FD contains a 2 KB RAM that is used to

store message objects. There are three different kinds

of message objects:

• Table 3-5: Transmit Message Objects used by the

TXQ and by TX FIFOs.

• Table 3-6: Receive Message Objects used by RX

FIFOs.

• Table 3-7: TEF objects.

Figure 3-2 illustrates how message objects are

mapped into RAM. The number of message objects for

the TEF, the TXQ, and for each FIFO is configurable.

Only the message objects for FIFO2 are shown in

detail. The number of data bytes per message object

(payload) is individually configurable for the TXQ and

each FIFO.

FIFOs and message objects can only be configured in

Configuration mode.

The TEF objects are allocated first. Space in RAM will

only be reserved if CiCON.STEF = 1.

Next the TXQ objects are allocated. Space in RAM will

only be reserved if CiCON.TXQEN = 1.

Next the message objects for FIFO1 through FIFO31

are allocated.

This highly flexible configuration results in an efficient

usage of the RAM.

The addresses of the message objects depend on the

selected configuration. The application doesn’t have to

calculate the addresses. The User Address field pro-

vides the address of the next message object to read

from or write to.

3.3.1

RAM ECC

The RAM is protected with an Error Correction Code

(ECC). The ECC logic supports Single Error Correc-

tion (SEC), and Double Error Detection (DED).

SEC/DED requires seven parity bits in addition to the

32 data bits.

Figure 3-3 shows the block diagram of the ECC logic.

3.3.1.1

ECC Enable and Disable

The

ECC

logic

can

enabled

setting

ECCCON.ECCEN. When ECC is enabled, the data

written to the RAM is encoded, and the data read from

RAM is decoded.

When the ECC logic is disabled, the data is written to

RAM, the parity bits are taken from ECCCON.PARITY.

This enables the testing of the ECC logic by the user.

During a read the parity bits are stripped out and the

data is read back unchanged.

3.3.1.2

RAM Write

During a RAM write, the Encoder calculates the parity

bits and adds the parity bits to the input data.

3.3.1.3

RAM READ

During a RAM read, the Decoder checks the output

data from RAM for consistency and removes the parity

bits. It corrects single bit errors and detects double bit

errors.

FIGURE 3-2:

MESSAGE MEMORY

ORGANIZATION

FIGURE 3-3:

ECC LOGIC

TEF

TX Queue

FIFO1

FIFO3

FIFO2: Message Object 0

FIFO2: Message Object 1

FIFO2: Message Object n

FIFO31

Encoder

Decoder

RAM 512x(32+7)

Write Data

D<31:0>

DE<38:0>

DR<38:0>

QR<38:0>

Read Data

Q<31:0>

ECCCON.ECCEN

ECCSTAT.SECIF

ECCSTAT.DEDIF

Data/Parity

P<6:0>

DP<38:0>

QR<31:0>

without Parity

ECC.PARITY

DO<31:0>

D<31:0>

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