W5500 datasheet(21/66 Pages) WIZNET

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W5500 Datasheet Version1.0.9

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2.3.2

Read Access in VDM

Figure 11. Read SPI Frame in VDM mode

Figure 11 shows the SPI Frame when external host accesses W5500 for reading

In VDM mode, the RWB signal is ‘0’ (Write), OM[1:0] is ‘00’ in SPI Frame Control

Phase. At this time the External Host assert (High-to-Low) SCSn signal before

transmitting SPI Frame.

Then the Host transmits Address and Control Phase all bits to W5500 through MOSI

signal. All bits are synchronized with the falling edge of the SCLK.

Then the Host receives all bits of Data Phase with synchronizing the rising edge of

Sampling SCLK through MISO signal.

After finishing the Data Phase receive, the Host de-asserts SCSn signal (Low-to-

High).

When SCSn is Low and the Data Phase continues to receive, the Sequential Data

Read can be supported.

MOSI

MISO

SCSn

SCLK

33 34

35 36 37 38

...

8N + 16

8N + 24

8-bit Data 2

...

8-bit Data N

SCSn Should be remained low until SPI Frame Transmit & Receive done.

SPI Frame End

SCSn

MOSI

MISO

SCLK

12 13 14

16bits Offset Address

17 18

20 21 22 23

25 26

27 28

29 30 31

8-bit Data 1

MODE0

MODE3

BSB[4:0]

RWB

OM[1:0]

R 0 0

SCSn shoud be remained low until SPI Frame Transmit & Receive done.

SPI Frame Start

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