công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

WM8742GEDS/V bảng dữ liệu(PDF) 26 Page - Cirrus Logic

tên linh kiện WM8742GEDS/V
Giải thích chi tiết về linh kiện  24-bit 192 kHz DAC with Advanced Digital Filtering
PDF  66 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8742GEDS/V bảng dữ liệu(HTML) 26 Page - Cirrus Logic

Back Button WM8742GEDS/V Datasheet HTML 22Page - Cirrus Logic WM8742GEDS/V Datasheet HTML 23Page - Cirrus Logic WM8742GEDS/V Datasheet HTML 24Page - Cirrus Logic WM8742GEDS/V Datasheet HTML 25Page - Cirrus Logic WM8742GEDS/V Datasheet HTML 26Page - Cirrus Logic WM8742GEDS/V Datasheet HTML 27Page - Cirrus Logic WM8742GEDS/V Datasheet HTML 28Page - Cirrus Logic WM8742GEDS/V Datasheet HTML 29Page - Cirrus Logic WM8742GEDS/V Datasheet HTML 30Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 26 / 66 page
background image
WM8742
26
Rev 4.4
Sample 1
Sample 2
LRCLK
BCLK
DINL
1/8fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
1/8fs
DINR
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 20 8FS Mode Right Justified Timing Requirements
In both modes the polarity of LRCLK can be switched using register bit LRP.
8FS MODE SAMPLING RATES
Since the data rate in 8FS mode is much faster than in standard PCM mode, there are restrictions on
the MCLK rate that can be used. Specifically, only 512fs and 768fs modes are permitted restricting
the sample rate to a maximum of 8x48kHz. The master clock should be synchronised with LRCLK,
although the WM8742 is tolerant of phase differences or jitter on this clock.
Unlike in normal PCM mode, the master clock detection circuit does not operate in 8FS mode. The
rate must be manually programmed using the control interface.
SAMPLING
RATE
LRCLK
FREQUENCY
(kHz)
MASTER CLOCK (MCLK)
FREQUENCY (MHz)
fs
8fs
512fs
768fs
32kHz
256
16.384
24.576
44.1kHz
352.8
22.5792
33.8688
48kHz
384
24.576
36.864
Table 12 Typical Relationships Between Master Clock Frequency and Sampling Rate in 8FS
Mode
AUDIO INTERFACE DAISY CHAINING
In daisy chain mode the DOUT pin outputs the audio data received on the DIN pin but delayed by two
times the input word length. When this output is connected to the DIN pin of the next device in the
chain, each WM8742 device will simultaneously sample different channel data in the same LRCLK
period. Daisy chaining is only available in DSP audio interface mode and is limited by a maximum
BCLK frequency of 24.576MHz.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8
Mode Control 2
08h
4
DOUT
0
Daisy Chaining Multiple devices
–
multichannel off one PCM feed.
0 = No Output
1 = Output on pin 23.
Table 13 Daisy Chaining Audio Data Output Control



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com