WM8742GEDSSLASHV datasheet(16/66 Pages) CIRRUS

16 / 66 page

WM8742

Rev 4.4

INTERNAL POWER ON RESET CIRCUIT

The WM8742 includes two internal Power On Reset (POR) circuits which are used to reset the digital

logic into a default state after power up and to allow the analogue circuits to power-up silently.

The digital POR circuit is powered from DVDD. This circuit monitors DVDD and asserts the internal

digital reset if DVDD are below the minimum DVDD threshold which will allow the digital logic to

function.

The analogue POR circuit is powered from AVDD. The circuit monitors AVDD, tri-stating the DAC

outputs and isolating the internal reference resistor strings from AVDDL and AVDDR until there is

sufficient AVDD voltage to allow the analogue DAC stages to function correctly.

AVDD

por_lo

VMIDL

AGND

Internal POR active

INTERNAL

ANALOGUE

PORB

Device Ready

Internal

POR active

No Power

POR

Undefined

por_hi

pord

Figure 7 AVDD Power up Sequence

Test Conditions

AVDD = 5V, AGND = 0V, TA = +25

oC, TA_max = +125oC, TA_min = -25oC, AVDDmax = 5.5V, AVDDmin = 4.5V

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply Input Timing Information

AVDD level to POR rising

edge (AVDD rising)

Vpor_hi

Measured from AGND

2.00

AVDD level to POR falling

edge (AVDD falling)

Vpor_lo

Measured from AGND

1.84

Table 6 Analogue POR Timing

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