WM8742GEDSSLASHV datasheet(11/66 Pages) CIRRUS

11 / 66 page

WM8742

Rev 4.4

TEST CONDITIONS

AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25

oC, 1kHz test signal, fs = 48kHz, MCLK = 512fs unless otherwise

stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Internal Analogue Filter

Bandwidth

-3dB

474

kHz

Passband edge response

20kHz

-0.0077

Analogue Output Levels

PCM full scale differential

output level

Into 10k

Ω load, 0dBFS input

VRMS

DSD Direct differential

output level

Into 10k

Ω load, 0dB

DSD input

0.948

VRMS

DSD Plus differential output

level

Into 10k

Ω load, 0dB

DSD input

0.991

VRMS

Minimum resistance load

To midrail or AC coupled

Ω

Maximum capacitance load

Output DC level

AVDD/2

Reference Levels

Potential divider resistance

AVDD to VMIDL/VMIDR and

VMIDL/VMIDR to AGND

Ω

Voltage at VMIDL/VMIDR

AVDD/2

Notes:

Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, me

asured ‘A’ weighted

over a 20Hz to 20kHz bandwidth.

All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher THD and lower

SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band

noise; although it is not audible it may affect dynamic specification values.

MASTER CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Master Clock Timing Information

MCLK Master clock pulse width high

tMCLKH

MCLK Master clock pulse width low

tMCLKL

MCLK Master clock cycle time

tMCLKY

MCLK Duty cycle

40:60

60:40

Table 1 MCLK Timing Requirements

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