ADC3541 datasheet(36/68 Pages) TI1

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7.3.5 Digital Interface

The ADC354x family supports two different CMOS output modes - parallel SDR/DDR output and serialized

CMOS output formats.

7.3.5.1 Parallel CMOS Output

The low power CMOS interface supports single data rate (SDR) and double data rate (DDR) output options. In

SDR and DDR output mode the output clock is generated inside the ADC354x. The different interface options

are configured using SPI register writes.

7.3.5.2 Serialized CMOS output

In this mode the output data is serialized and transmitted over 2 or 1 wires. Due to CMOS output speed limitation

this mode is only available for reduced output data rates. This mode is similar to the multi-SPI interface.

7.3.5.2.1 SDR Output Clocking

The ADC354x provides a SDR output clocking option for all serial CMOS output modes (including decimation)

which is enabled using the SPI interface. In serial CMOS mode by default the data is output on rising and falling

edge of DCLK. In SDR clocking mode, DCLKIN has to be twice as fast as the default DCLKIN so that the output

data are clocked out only on DCLK rising edge.

Internally DCLKIN is divided by 2 for data processing and this operation can add 1 extra clock cycle latency to

the ADC latency.

Continous

Clock

Sample N

Latency (2 clock cycles)

Sample N+4

DCLKIN

tAD

tPD

DCLK

Sample N+1

Sample N+2

Sample N+3

Sample N+5

Sample N+6

Sample N

D12

D11

FCLK

Sample N+1

Sample N+2

Sample N-1

tCD

DCLKIN

SDR

DCLK

SDR

Figure 7-36. SDR Output Clocking

ADC3541

SBAS840 – JULY 2020

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