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ADC3541 bảng dữ liệu(PDF) 26 Page - Texas Instruments |
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ADC3541 bảng dữ liệu(HTML) 26 Page - Texas Instruments |
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26 / 68 page ![]() 7.3.4 Digital Down Converter The ADC354x includes an optional on-chip digital down conversion (DDC) decimation filter that can be enabled via SPI register setting. It supports complex decimation by 2, 4, 8, 16 and 32 using a digital mixer and a 32-bit numerically controlled oscillator (NCO) as shown in Figure 7-17. Furthermore it supports a mode with real decimation where the complex mixer is bypassed (NCO should be set to 0 for lowest power consumption) and the digital filter acts as a low pass filter. Internally the decimation filter calculations are performed with a 20-bit resolution in order to avoid any SNR degradation due to quantization noise. The output formatter (Section 7.3.5.4) truncates to the selected resolution prior to outputting the data on the digital interface. ADC Filter I SYNC NCO 32bit Digital Interface I N Q Q Figure 7-17. Internal Digital Decimation Filter ADC3541 SBAS840 – JULY 2020 www.ti.com 26 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADC3541 |
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