LPC55S6X datasheet(47/128 Pages) NXP

47 / 128 page

LPC55S6x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.9 — 10 February 2020

47 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.21 RAM configuration

Table 9 describes the RAM configuration for the LPC55S6x.

7.22 System control

7.22.1 Clock sources

The LPC55S6x supports 2 external and 3 internal clock sources:

• Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96 MHz

output, and a 12 MHz output (divided down from the selected higher frequency) that

can be used as a system clock. The FRO is trimmed to +/- 2% accuracy over the

entire voltage and temperature range. The FRO 12 MHz oscillator provides the

default clock at reset and provides a clean system clock shortly after the supply pins

reach operating voltage.

• 32 kHz Internal Free Running Oscillator FRO. The FRO is trimmed to +/- 2% accuracy

over the entire voltage and temperature range.

Internal low power oscillator (FRO 1 MHz). The FRO is trimmed to +/- 15% accuracy

over the entire voltage and temperature range.

• Crystal oscillator with an operating frequency of 1 MHz to 32 MHz. Option for external

clock input (bypass mode) for clock frequencies of up to 24 MHz

• Crystal oscillator with 32.768 KHz operating frequency. Option for external clock input

(bypass mode) for clock frequencies of up to 100 kHz

• Each crystal oscillator has one embedded capacitor bank which can be used as an

integrated load capacitor. Using APIs, the capacitor banks on each crystal pin can

tune the frequency for crystals with a Capacitive Load (CL) which conserves board

space and reduces costs.

7.22.2 PLL (PLL0 and PLL1)

PLL0 and PLL1 allows CPU operation up to the maximum CPU rate without the need for a

high-frequency external clock. PLL0 and PLL1 can run from the internal FRO 12 MHz

output, the external oscillator, internal FRO 1 MHz output, or the 32.768 KHz RTC

oscillator.

The system PLL accepts an input clock frequency in the range of 2 kHz - 150 MHz. The

input frequency is multiplied up to a high frequency with a Current Controlled Oscillator

(CCO). The PLL can be enabled or disabled by software.

Table 9.

RAM Configuration

RAM Total

RAM-X (KB)

RAM0 (KB)

RAM1 (KB)

RAM2 (KB)

RAM3 (KB)

RAM4 (KB)

USB-RAM (KB)

320 KB

devices

256 KB

devices

144 KB

devices

LPC55S6X bảng dữ liệu(PDF) 47 Page - NXP Semiconductors

LPC55S6X bảng dữ liệu(HTML) 47 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL