XRT7250 datasheet(403/463 Pages) EXAR

403 / 463 page

XRT7250

áç

DS3/E3 FRAMER IC

REV. 1.1.1

384

mission of a LAPD Message Interrupt to the

Microcontroller/Microprocessor. Once the

XRT7250 Framer IC generates this interrupt, it

will do the following.

• Assert the Interrupt Output pin (INT) by toggling it

“Low”.

• Set Bit 0 (TxLAPD Interrupt Status) within the TxE3

LAPD Status and Interrupt Register, to “1” as illus-

trated below.

The purpose of this interrupt is to alert the Microcon-

troller/MIcroprocessor that the LAPD Transmitter has

completed its transmission of a given LAPD (or PM-

DL) Message, and is now ready to transmit the next

PMDL Message, to the Remote Terminal Equipment.

6.3

THE RECEIVE SECTION OF THE XRT7250 (E3

MODE OPERATION)

When the XRT7250 has been configured to operate

in the E3 Mode, the Receive Section of the XRT7250

consists of the following functional blocks.

• Receive LIU Interface block

• Receive HDLC Controller block

• Receive E3 Framer block

• Receive Overhead Data Output Interface block

• Receive Payload Data Output Interface block

Figure 185 presents a simple illustration of the Re-

ceive Section of the XRT7250 Framer IC.

Each of these functional blocks will be discussed in

detail in this document.

6.3.1

The Receive E3 LIU Interface Block

The purpose of the Receive E3 LIU Interface block is

two-fold:

1. To receive encoded digital data from the E3 LIU

IC.

TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

TXDL Start

TXDL Busy

TxLAPD

Interrupt

Enable

TxLAPD

Interrupt

Status

R/W

RUR

000

001

FIGURE 185. A SIMPLE ILLUSTRATION OF THE RECEIVE SECTION OF THE XRT7250, WHEN IT HAS BEEN CONFIG-

URED TO OPERATE IN THE

E3 MODE

Receive

Payload Data

Input

Interface Block

Receive DS3/E3

Framer Block

Receive LIU

Interface

Block

RxSer

RxNib[3:0]

RxClk

RxPOS

RxNEG

RxLineClk

Receive Overhead

Input

Interface Block

RxOHClk

RxOHInd

RxOH

RxOHEnable

RxOHFrame

RxFrame

Rx E3 HDLC

Controller/Buffer

Rx E3 HDLC

Controller/Buffer

From Microprocessor

Interface Block

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