XRT7250 datasheet(323/463 Pages) EXAR

323 / 463 page

XRT7250

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DS3/E3 FRAMER IC

REV. 1.1.1

304

Where: Flag Sequence = 0x7E

SAPI + CR + EA = 0x3C or 0x3E

TEI + EA = 0x01

Control = 0x03

The 16 bit FCS is calculated using CRC-16, x16 +

x12 + x5 + 1

The local µP (at the remote terminal), while assem-

bling the LAPD Message frame, will insert an addi-

tional byte at the beginning of the information (pay-

load) field. This first byte of the information field indi-

cates the type and size of the message being trans-

ferred. The value of this information field and the

corresponding message type/size follow:

CL Path Identification

= 0x38 (76 bytes)

IDLE Signal Identification = 0x34 (76 bytes)

Test Signal Identification = 0x32 (76 bytes)

ITU-T Path Identification = 0x3F (82 bytes)

Enabling and Configuring the LAPD Receiver

Before the LAPD Receiver can begin to receive and

process incoming LAPD Message frames, the user

must do two things.

1. Enabling the LAPD Receiver

The LAPD Receiver must be enabled before it can

begin receiving and processing any LAPD Message

frames. The LAPD Receiver can be enabled by writ-

ing a “1” to Bit 2 (RxLAPD Enable) of the Rx E3 LAPD

Control Register, as indicated below.

)

Once the LAPD Receiver has been enabled, it will be-

gin searching for the Flag Sequence octet (0x7E), in

the “N” bit-fields within each incoming E3 frame.

When the LAPD Receiver finds the flag sequence

byte, it will assert the Flag Present bit (Bit 0) within

the Rx E3 LAPD Status Register, as depicted below.

FIGURE 142. LAPD MESSAGE FRAME FORMAT

Flag Sequence (8 bits)

SAPI (6-bits)

C/R

TEI (7 bits)

Control (8-bits)

76 or 82 Bytes of Information (Payload)

FCS - MSB

FCS - LSB

Flag Sequence (8-bits)

RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

RxLAPD

Enable

RxLAPD

Interrupt Enable

RxLAPD

Interrupt Enable

R/W

RUR

00000

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