XRT7250 datasheet(198/463 Pages) EXAR

198 / 463 page

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

179

4.2.6

Transmit Section Interrupt Processing

The Transmit Section of the XRT7250 can generate

an interrupt to the Microcontroller/Microprocessor for

the following two reasons.

• Completion of Transmission of FEAC Message

• Completion of Transmission of LAPD Message

4.2.6.1

Enabling Transmit Section Interrupts

As mentioned in Section 1.6, the Interrupt Structure,

within the XRT7250 contains two hierarchical levels:

• Block Level

• Source Level

The Block Level

The Enable State of the Block Level for the Transmit

Section Interrupts dictates whether or not interrupts

(if enabled at the source level), are actually enabled.

The user can enable or disable these Transmit Sec-

tion interrupts, at the Block Level by writing the appro-

priate data into Bit 1 (Tx DS3/E3 Interrupt Enable)

within the Block Interrupt Enable register (Address =

0x04), as illustrated below.

FIGURE 70. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG

ARE CONFIGURED TO BE UPDATED ON THE RISING EDGE OF

TXLINECLK

TxLineClk

TxPOS

TxNEG

t32

t30

t33

FIGURE 71. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG

ARE CONFIGURED TO BE UPDATED ON THE FALLING EDGE OF

TXLINECLK

TxLineClk

TxPOS

TxNEG

t31

t32

t33

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