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XRT7250 bảng dữ liệu(PDF) 147 Page - Exar Corporation

tên linh kiện XRT7250
Giải thích chi tiết về linh kiện  DS3/E3 FRAMER IC
PDF  463 Pages
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nhà sản xuất  EXAR [Exar Corporation]
Trang chủ  http://www.exar.com
Logo EXAR - Exar Corporation

XRT7250 bảng dữ liệu(HTML) 147 Page - Exar Corporation

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XRT7250
DS3/E3 FRAMER IC
áç
áç
áç
áç
REV. 1.1.1
128
Fi = Frame synchronization bit with logic value i
P = Parity bit
Mi = Multiframe synchronization bit with logic value i
AIC = Application Identification Channel
NA = reserved for network application
FEAC = Far End Alarm and Control
DL = Data Link
CP = CP (Path)-bit parity
FEBE = Far End Block Error
UDL = User Data Link
X = Signaling bit for network control
I = Payload Information (84 bit packets)
Fi = Frame synchronization bit with logic value i
Cij = jth stuff code bit of ith channel
P = Parity bit
Mi = multiframe synchronization bit with logic values i
The user can choose between these two frame for-
mats, by writing the appropriate data to bit 2 of the
Framer Operating Mode Register (Address = 0x00),
as depicted below.
Table 16 lists the relationship between the value of
the this bit-field and the resulting DS3 Frame Format.
NOTE: This bit setting also configures the frame format for
both the Transmit and Receive Section of the XRT7250.
Each of the two DS3 Frame Formats, as presented in
Figure 40 and Figure 41, constitute an M-frame (or a
full DS3 Frame). Each M-frame consists of 7 - 680 bit
F-frames (sometimes referred to as, subframes). In
Figure 40 and 41, each F-frame is represented by
the individual rows of payload and overhead bits.
Each F-frame can be further divided into 8 blocks of
85 bits, with 84 of the 85 bits available for payload in-
formation and the remaining one bit used for frame
overhead.
Differences Between the M13 and C-Bit Parity
Frame Formats
The frame formats for M13 and C-bit Parity are very
similar. However, the main difference between these
FIGURE 41. DS3 FRAME FORMAT FOR M13
X
IF1
IC11
IF0
IC12
IF0
IC13
IF1
I
I
X
IF1
IC21
IF0
IC22
IF0
IC23
IF1
I
P
IF1
IC31
IF0
IC32
IF0
IC33
IF1
I
P
IF1
IC41
IF0
IC42
IF0
IC43
IF1
I
M0
IF1
IC51
IF0
IC52
IF0
IC53
IF1
I
M1
IF1
IC61
IF0
IC62
IF0
IC63
IF1
I
M0
IF1
IC71
IF0
IC72
IF0
IC73
IF1
I
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6BIT 5BIT 4BIT 3
BIT2BIT 1BIT 0
Local Loopback
DS3/E3*
Internal LOS
Enable
RESET
Interrupt
Enable Reset
Frame Format
TimRefSel[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
1x
0
x
xx
x
TABLE 16: THE RELATIONSHIP BETWEEN THE CONTENT
OF
BIT 2, (C-BIT PARITY*/M13) WITHIN THE FRAMER
OPERATING MODE REGISTER AND THE RESULTING DS3
FRAMING FORMAT
BIT 2
DS3 FRAME FORMAT
0
C-Bit Parity
1M13



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