XRT7250 datasheet(133/463 Pages) EXAR

133 / 463 page

XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

114

The XRT7250 Framer Interrupt Block comes

equipped with the following registers to support the

servicing of these potential interrupt request sources.

Table 6, 7 , and 8 lists these registers, and their ad-

dresses, within the Framer IC for DS3, E3 (ITU-T

G.832) and E3 (ITU-T G.751) framing formats.

TABLE 5: LIST OF ALL OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS WITHIN THE XRT7250

FRAMER DEVICE

FUNCTION SECTION

INTERRUPTING CONDITION

Transmit Section

FEAC Message Transfer Complete (DS3, C-Bit Parity Only)

LAPD Message frame Transfer Complete (DS3, C-Bit Parity, All E3)

Receive Section

Change of Status on Receive LOS, OOF, AIS Idle Detection

Validation and removal of received FEAC Code (DS3, C-Bit Parity Only)

New PMDL Message in Receive LAPD Message Buffer.

Detection of Parity Errors (e.g., P-Bit, CP-Bit, BIP-4 and BIP-8 Errors)

Detection of Framing Bit/Byte Errors.

Framer Chip Level

One-Second Interrupt

TABLE 6: A LISTING OF THE XRT7250 FRAMER DEVICE INTERRUPT BLOCK REGISTERS (FOR DS3 APPLICATIONS)

ADDRESS LOCATION

0 x 04

Block Interrupt Enable Register

0 x 05

Block Interrupt Status Register

0 x 12

RxDS3 Interrupt Enable Register

0 x 13

RxDS3 Interrupt Status Register

0 x 17

RxDS3 FEAC Interrupt Enable/Status Register

0 x 18

RxDS3 LAPD Control Register

0 x 31

TxDS3 FEAC Configuration and Status Register

0 x 34

TxDS3 LAPD Status/Interrupt Register

TABLE 7: A LISTING OF THE XRT7250 FRAMER DEVICE INTERRUPT BLOCK REGISTERS (FOR E3, ITU-T G.832

APPLICATIONS)

ADDRESS LOCATION

0 x 04

Block Interrupt Enable Register

0 x 05

Block Interrupt Status Register

0 x 12

RxE3 Interrupt Enable Register -1

0 x 13

RxE3 Interrupt Enable Register -2

0 x 14

RxE3 Interrupt Status Register - 1

0 x 15

RxE3 Interrupt Status Register - 2

0 x 18

RxE3 LAPD Control Register

0 x 34

TxE3 LAPD Status/Interrupt Status

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