XRT7250 datasheet(126/463 Pages) EXAR

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

107

This Reset-upon-Read register, along with the PMON

CP-Bit Error Count Register - LSB (Address = 0x59)

contains a 16-bit representation of the number of CP-

bit Errors that have been detected by the Receive

DS3 Framer block (within the chip), since the last

read of these registers. This register contains the

MSB (or Upper-Byte) value of this 16 bit expression.

2.3.8.10 PMON CP-Bit Error Event Count Regis-

ter - LSB

This Reset-upon-Read register, along with the PMON

CP-Bit Error Count Register - MSB (Address = 0x58)

contains a 16-bit representation of the number of CP-

bit Errors that have been detected by the Receive

DS3 Framer block (within the chip), since the last

read of these registers. This register contains the

LSB (or Lower-Byte) value of this 16 bit expression.

2.3.8.11 PMON Holding Register

Each of the PMON registers are 16 bit Reset-upon-

Read registers. More specifically, whenever the Mi-

croprocessor intends to read a PMON register, there

are two things to bear in mind.

1. This Microprocessor is going to require two read

accesses in order read out the full 16-bit expres-

sion of these PMON registers.

2. The entire 16-bit expression (of a given PMON

the Microprocessor has completed its first read

access to the PMON register.

Hence, the contents of the other byte (of the partially

read PMON register) will reside within the PMON

Holding register.

2.3.8.12 One-Second Error Status Register

PMON CP-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X58)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

CP-Bit Error Count - High Byte

RUR

0000

000

PMON CP-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X59)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

CP-Bit Error Count - Low Byte

RUR

0000

000

PMON HOLDING REGISTER (ADDRESS = 0X6C)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

PMON Holding Value

RUR

0000

000

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