XRT7250 datasheet(119/463 Pages) EXAR

119 / 463 page

XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

100

contents of this register must be set to all "0’s" (the

default value).

2.3.6.25 Transmit E3 BIP-8 Error Mask Register

(E3, ITU-T G.832)

This Read/Write bit-field allows the user to insert er-

rors into EM (Error Monitor) octet of each outbound

E3 frame. The user may wish to do this for equip-

ment testing purposes. Prior to transmission, the

Transmit E3 Framer reads in the EM byte, and per-

forms an XOR operation with it and the contents of

this register. The results of this operation are written

back into the EM octet position, in each outbound E3

frame. Consequently, to insure errors are not injected

into the EM octet of the outbound E3 frames, the con-

tents of this register must be set to all "0’s" (the de-

fault value).

2.3.7

Transmit E3 Framer Configuration Regis-

ters (ITU-T G.751)

2.3.7.1

Transmit E3 Configuration Register

(ITU-T G.751)

Bit 7 - TxBIP-4 Enable

This Read/Write bit-field permits the user to configure

the Transmit Section of the Framer IC, to compute an

insert the BIP-4 value into each outbound E3 frame.

Setting this bit-field to "0", configures the Transmit

Section of the Framer IC to NOT compute and insert

the BIP-4 value into each outbound E3 frame. In-

stead these four bits will contain data that has been

input via the Input Interface.

Setting this bit-field to "1", configures the Transmit

Section of the Framer IC to compute and insert the

BIP-4 value into each outbound E3 frame.

NOTE: For more information on these BIP-4 Calculations,

please see Section 4.2.4.2.2.

Bit 6, 5, TxASourceSel[1:0]

These two Read/Write bit-fields combine to specify

the source of the A-bit, within each outbound E3

frame. The relationship between these two bit-fields

and the resulting source of the A Bit is tabulated be-

low.

TXE3 BIP-8 ERROR MASK REGISTER (ADDRESS = 0X4A)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

TxBIP-8_Error_Mask_Byte[7:0]

R/W

000

TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

BIP-4

Enable

TxASourceSel[1:0]

TxNSourceSel[1:0]

Tx AIS

Enable

Tx LOS

Enable

Tx FAS

Source

Select

R/W

000

TXASOURCESEL[1:0]

SOURCE OF A BIT

TxE3 Service Bits Register (Address = 0x35)

Transmit Overhead Data Input Interface

Transmit Payload Data Input Interface

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