XRT83SL34 datasheet(66/80 Pages) EXAR

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XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

TABLE 36: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION

1000001

NAME

FUNCTION

TYPE

RESET

VALUE

BIT #

E1arben

E1 Arbitrary Pulse Enable

This bit is used to enable the Arbitrary Pulse Generators for

shaping the transmit pulse shape when E1 mode is selected.

If this bit is set to "1", all 8 channels will be configured for the

Arbitrary Mode. However, each channel is individually con-

trolled by programming the channel registers 0xn8 through

0xnF, where n is the number of the channel.

"0" = Disabled (Normal E1 Pulse Shape ITU G.703)

"1" = Arbitrary Pulse Enabled

R/W

CLKSEL2

Clock Select Inputs for Master Clock Synthesizer bit 2:

In Host mode, CLKSEL[2:0] are input signals to a programma-

ble frequency synthesizer that can be used to generate a mas-

ter clock from an external accurate clock source according to

the following table;

In Hardware mode, the state of these signals are ignored and

the master frequency PLL is controlled by the corresponding

Hardware pins.

R/W

CLKSEL1

Clock Select inputs for Master Clock Synthesizer bit 1:

See description of bit D6 for function of this bit.

R/W

CLKSEL0

Clock Select inputs for Master Clock Synthesizer bit 0:

See description of bit D6 for function of this bit.

R/W

2048

1544

MC LKE1

kH z

128

256

128

2048

1544

M CLKT1

kH z

1544

2048

1544

2048

CLKOUT/

kH z

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

CLKSEL0

CLKSEL1

CLKSEL2

1544

2048

1544

M C LK RATE

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