XRT83SL34 datasheet(36/80 Pages) EXAR

36 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

N+1 REDUNDANCY

N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention,

external relays are necessary when using this redundancy scheme. The advantage of relays is that they create

complete isolation between the primary cards and the backup card. This allows all transmitters and receivers

on the primary cards to be configured in internal impedance mode, providing one bill of materials for all

interface modes of operation. The transmit and receive sections of the XRT83SL34 are described separately.

TRANSMIT

For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode

providing one bill of materials for T1/E1/J1. The transmitters on the backup card do not have to be tri-stated. To

swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A

0.68

µF capacitor is used in series with TTIP for blocking DC bias. See Figure 16 for a simplified block diagram

of the transmit section for an N+1 redundancy scheme.

NOTE: For simplification, the over voltage protection circuitry was omitted.

FIGURE 16. SIMPLIFIED BLOCK DIAGRAM - TRANSMIT SECTION FOR N+1 REDUNDANCY

B a ckp lane In te rface

P rim ary C a rd

X R T 83S L3 4

Line In te rface C a rd

0.68

µF

T 1 /E 1 Line

P rim ary C a rd

X R T 83S L3 4

P rim ary C a rd

X R T 83S L3 4

B a ckup C a rd

X R T 83S L3 4

T 1 /E 1 Line

T xT S EL =1 , In te rn a l

1:2 or 1:2.45

0.68

µF

0.68

µF

0.68

µF

1:2 or 1:2.45

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