RA4W1 datasheet(63/105 Pages) RENESAS

63 / 105 page

R01DS0359EJ0100 Rev.1.00

Page 63 of 105

Mar 31, 2020

RA4W1 Datasheet

2. Electrical Characteristics

Note 1.

tPcyc: PCLKA cycle.

Note 2.

N is set as an integer from 1 to 8 by the SPCKD register.

Note 3.

N is set as an integer from 1 to 8 by the SSLND register.

Note 4.

The upper limit of RSPCK is 16 MHz.

Figure 2.50

SPI clock timing

SPI

SSL rise and fall

time

Output

2.7 V or above

tSSLr,

tSSLf

-10

Figure 2.51 to

Figure 2.56

2.4 V or above

1.8 V or above

Input

µs

Slave access time

2.4 V or above

tSA

-2 × tPcyc + 100 ns

Figure 2.55 and

Figure 2.56

1.8 V or above

2 × tPcyc + 140

Slave output release time

2.4 V or above

tREL

-2 × tPcyc + 100 ns

1.8 V or above

2 × tPcyc + 140

Table 2.37

SPI timing (2 of 2)

Conditions: Middle drive output is selected in the Port Drive Capability in PmnPFS register

Parameter

Symbol

Min

Max

Unit*1

Test conditions

RSPCKn

master select

output

RSPCKn

slave select input

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

n = A or B

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