RA4W1 datasheet(62/105 Pages) RENESAS

62 / 105 page

R01DS0359EJ0100 Rev.1.00

Page 62 of 105

Mar 31, 2020

RA4W1 Datasheet

2. Electrical Characteristics

2.3.9

SPI Timing

Table 2.37

SPI timing (1 of 2)

Conditions: Middle drive output is selected in the Port Drive Capability in PmnPFS register

Parameter

Symbol

Min

Max

Unit*1

Test conditions

SPI

RSPCK clock cycle

Master

tSPcyc

2*4

4096

tPcyc

Figure 2.50

Slave

4096

RSPCK clock high

pulse width

Master

tSPCKWH (tSPcyc – tSPCKr

– tSPCKf) / 2 – 3

-ns

Slave

3 × tPcyc

RSPCK clock low

pulse width

Master

tSPCKWL (tSPcyc – tSPCKr

– tSPCKf) / 2 – 3

-ns

Slave

3 × tPcyc

RSPCK clock rise

and fall time

Output

2.7 V or above

tSPCKr,

tSPCKf

-10

2.4 V or above

1.8 V or above

Input

µs

Data input setup

time

Master

tSU

Figure 2.51 to

Figure 2.56

Slave

2.4 V or above

1.8 V or above

Data input hold time Master

(RSPCK is PCLKA/2)

tHF

Master

(RSPCK is other than

above.)

tPcyc

Slave

SSL setup time

Master

1.8 V or above

tLEAD

-30 + N × tSpcyc*2

-ns

Slave

6 × tPcyc

SSL hold time

Master

tLAG

-30 + N × tSpcyc*3

Slave

6 × tPcyc

Data output delay

Master

2.7 V or above

tOD

-14

Figure 2.51 to

Figure 2.56

2.4 V or above

1.8 V or above

Slave

2.7 V or above

2.4 V or above

1.8 V or above

Data output hold

time

Master

tOH

Slave

Successive

transmission delay

Master

tTD

tSPcyc + 2 × tPcyc

8 × tSPcyc

+ 2 × tPcyc

Slave

6 × tPcyc

MOSI and MISO

rise and fall time

Output

2.7 V or above

tDr, tDf

-10

2.4 V or above

1.8 V or above

Input

µs

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