STM8S datasheet(318/467 Pages) STMICROELECTRONICS

tên linh kiện	STM8S

Giải thích chi tiết về linh kiện	STM8S Series and STM8AF Series 8-bit microcontrollers

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Inter-integrated circuit (I2C) interface

RM0016

318/467

DocID14587 Rev 14

21.7.13

TRISE register (I2C_TRISER)

Address offset: 0x0D

Reset value: 0x02

654

3210

Reserved

TRISE[5:0]

Bits 7:6 Reserved

Bits 5:0 TRISE[5:0] Maximum rise time in Fast/Standard mode (Master mode)

These bits should provide the maximum duration of the SCL feedback loop in master mode. The

purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.

These bits must be programmed with the maximum SCL rise time given in the I2C bus specification,

incremented by 1.

For instance: in standard mode, the maximum allowed SCL rise time is 1000 ns.

If the value in the I2C_FREQR register = 08h, then tMASTER = 125 ns therefore the TRISE[5:0] bits

must be programmed with 0x09.

(1000 ns / 125 ns = 8 + 1)

The filter value can also be added to TRISE[5:0].

If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order to

respect the tHIGH parameter.

Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).

STM8S bảng dữ liệu(PDF) 318 Page - STMicroelectronics