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STM8S bảng dữ liệu(PDF) 282 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  STM8S Series and STM8AF Series 8-bit microcontrollers
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STM8S bảng dữ liệu(HTML) 282 Page - STMicroelectronics

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Serial peripheral interface (SPI)
RM0016
282/467
DocID14587 Rev 14
20.4
SPI registers
20.4.1
SPI control register 1 (SPI_CR1)
Address offset: 0x00
Reset value: 0x00
765
432
10
LSBFIRST
SPE
BR [2:0]
MSTR
CPOL
CPHA
rw
rw
rw
rw
rw
rw
Bit 7 LSBFIRST: Frame format (1)
0: MSB is transmitted first
1: LSB is transmitted first
Bit 6 SPE: SPI enable (2)
0: Peripheral disabled
1: Peripheral enabled
Bits 5:3 BR[2:0]: Baud rate control
000: fMASTER/2
001: fMASTER/4
010: fMASTER/8
011: fMASTER/16
100: fMASTER/32
101: fMASTER/64
110: fMASTER/128
111: fMASTER/256
Note: These bits should not be changed when the communication is ongoing.
Bit 2 MSTR: Master selection (1)
0: Slave configuration
1: Master configuration
Bit1 CPOL: Clock polarity (1)
0: SCK to 0 when idle
1: SCK to 1 when idle
Bit 0 CPHA: Clock phase (1)
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
1. This bit should not be changed when the communication is ongoing.
2. When disabling the SPI, follow the procedure described in Section 20.3.8: Disabling the SPI on page 277



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